Fix reset and minor efficiency improvement + gitignore

.gitignore

@@ -0,0 +1,3 @@
+out/
+build
+test

build

@@ -1,2 +0,0 @@
-mkdir -p out
-iverilog -o out/sim simple_fifo.v fifo_tb.v

fifo_tb.v

@@ -1,3 +1,4 @@
+`timescale 100ps/1ps
 module fifo_tb;
 
 reg reset_n;
@@ -21,16 +22,18 @@ simple_fifo dut (
 
 initial begin
   clk = 1'b0;
-  reset_n = 1'b1;
-  repeat(4) #10 clk = ~clk;
   reset_n = 1'b0;
+  repeat(4) #10 clk = ~clk;
+  reset_n = 1'b1;
   forever #10 clk = ~clk; // generate a clock
 end
 
 reg [15:0] tmp;
 initial begin
   data_in = 16'h0; // initial value
-  @(negedge reset_n); // wait for reset
+  fifo_push = 1'b0;
+  fifo_pop = 1'b0;
+  @(posedge reset_n); // wait for reset
   data_in = 16'hffff;
   repeat (8) begin
     @(posedge clk);

out/sim

@@ -1,372 +0,0 @@
-#! /usr/local/Cellar/icarus-verilog/10.1.1/bin/vvp
-:ivl_version "10.1 (stable)" "(v10_1_1)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision + 0;
-:vpi_module "system";
-:vpi_module "vhdl_sys";
-:vpi_module "v2005_math";
-:vpi_module "va_math";
-S_0x7fa2f94081a0 .scope module, "fifo_tb" "fifo_tb" 2 1;
- .timescale 0 0;
-v0x7fa2f942c150_0 .var "clk", 0 0;
-v0x7fa2f942c210_0 .var "data_in", 15 0;
-v0x7fa2f942c2a0_0 .net "data_out", 15 0, v0x7fa2f942bb50_0;  1 drivers
-v0x7fa2f942c350_0 .net "empty", 0 0, v0x7fa2f942bbe0_0;  1 drivers
-v0x7fa2f942c400_0 .var "fifo_pop", 0 0;
-v0x7fa2f942c4d0_0 .var "fifo_push", 0 0;
-v0x7fa2f942c560_0 .net "full", 0 0, v0x7fa2f942bcb0_0;  1 drivers
-v0x7fa2f942c610_0 .var "reset_n", 0 0;
-v0x7fa2f942c6c0_0 .var "tmp", 15 0;
-E_0x7fa2f9415f70 .event negedge, v0x7fa2f9417170_0;
-E_0x7fa2f9415e20 .event negedge, v0x7fa2f942bf80_0;
-S_0x7fa2f941c480 .scope module, "dut" "simple_fifo" 2 9, 3 4 0, S_0x7fa2f94081a0;
- .timescale 0 0;
-    .port_info 0 /INPUT 1 "clk"
-    .port_info 1 /INPUT 1 "reset_n"
-    .port_info 2 /INPUT 1 "push"
-    .port_info 3 /INPUT 1 "pop"
-    .port_info 4 /INPUT 16 "data_in"
-    .port_info 5 /OUTPUT 16 "data_out"
-    .port_info 6 /OUTPUT 1 "full"
-    .port_info 7 /OUTPUT 1 "empty"
-P_0x7fa2f9403670 .param/l "DEPTH" 0 3 5, +C4<00000000000000000000000000001000>;
-P_0x7fa2f94036b0 .param/l "WIDTH" 0 3 6, +C4<00000000000000000000000000010000>;
-v0x7fa2f9417170_0 .net "clk", 0 0, v0x7fa2f942c150_0;  1 drivers
-v0x7fa2f942ba20 .array "data", 0 7, 15 0;
-v0x7fa2f942bac0_0 .net "data_in", 15 0, v0x7fa2f942c210_0;  1 drivers
-v0x7fa2f942bb50_0 .var "data_out", 15 0;
-v0x7fa2f942bbe0_0 .var "empty", 0 0;
-v0x7fa2f942bcb0_0 .var "full", 0 0;
-v0x7fa2f942bd40_0 .net "pop", 0 0, v0x7fa2f942c400_0;  1 drivers
-v0x7fa2f942bdd0_0 .net "push", 0 0, v0x7fa2f942c4d0_0;  1 drivers
-v0x7fa2f942be70_0 .var "rd_ptr", 2 0;
-v0x7fa2f942bf80_0 .net "reset_n", 0 0, v0x7fa2f942c610_0;  1 drivers
-v0x7fa2f942c020_0 .var "wr_ptr", 2 0;
-E_0x7fa2f9416e90 .event posedge, v0x7fa2f9417170_0;
-    .scope S_0x7fa2f941c480;
-T_0 ;
-    %wait E_0x7fa2f9416e90;
-    %load/vec4 v0x7fa2f942bf80_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.0, 8;
-    %pushi/vec4 0, 0, 3;
-    %assign/vec4 v0x7fa2f942be70_0, 0;
-    %pushi/vec4 0, 0, 3;
-    %assign/vec4 v0x7fa2f942c020_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bcb0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v0x7fa2f942bbe0_0, 0;
-    %jmp T_0.1;
-T_0.0 ;
-    %load/vec4 v0x7fa2f942bdd0_0;
-    %load/vec4 v0x7fa2f942bcb0_0;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.2, 8;
-    %load/vec4 v0x7fa2f942bac0_0;
-    %load/vec4 v0x7fa2f942c020_0;
-    %pad/u 5;
-    %ix/vec4 3;
-    %ix/load 4, 0, 0; Constant delay
-    %assign/vec4/a/d v0x7fa2f942ba20, 0, 4;
-    %load/vec4 v0x7fa2f942c020_0;
-    %addi 1, 0, 3;
-    %store/vec4 v0x7fa2f942c020_0, 0, 3;
-    %load/vec4 v0x7fa2f942c020_0;
-    %load/vec4 v0x7fa2f942be70_0;
-    %cmp/e;
-    %jmp/0xz  T_0.4, 4;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v0x7fa2f942bcb0_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bbe0_0, 0;
-    %jmp T_0.5;
-T_0.4 ;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bcb0_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bbe0_0, 0;
-T_0.5 ;
-T_0.2 ;
-    %load/vec4 v0x7fa2f942bd40_0;
-    %load/vec4 v0x7fa2f942bbe0_0;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.6, 8;
-    %load/vec4 v0x7fa2f942be70_0;
-    %pad/u 5;
-    %ix/vec4 4;
-    %load/vec4a v0x7fa2f942ba20, 4;
-    %assign/vec4 v0x7fa2f942bb50_0, 0;
-    %load/vec4 v0x7fa2f942be70_0;
-    %addi 1, 0, 3;
-    %store/vec4 v0x7fa2f942be70_0, 0, 3;
-    %load/vec4 v0x7fa2f942c020_0;
-    %load/vec4 v0x7fa2f942be70_0;
-    %cmp/e;
-    %jmp/0xz  T_0.8, 4;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bcb0_0, 0;
-    %pushi/vec4 1, 0, 1;
-    %assign/vec4 v0x7fa2f942bbe0_0, 0;
-    %jmp T_0.9;
-T_0.8 ;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bcb0_0, 0;
-    %pushi/vec4 0, 0, 1;
-    %assign/vec4 v0x7fa2f942bbe0_0, 0;
-T_0.9 ;
-T_0.6 ;
-T_0.1 ;
-    %jmp T_0;
-    .thread T_0;
-    .scope S_0x7fa2f94081a0;
-T_1 ;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c150_0, 0, 1;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v0x7fa2f942c610_0, 0, 1;
-    %pushi/vec4 4, 0, 32;
-T_1.0 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_1.1, 5;
-    %jmp/1 T_1.1, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %delay 10, 0;
-    %load/vec4 v0x7fa2f942c150_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c150_0, 0, 1;
-    %jmp T_1.0;
-T_1.1 ;
-    %pop/vec4 1;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c610_0, 0, 1;
-T_1.2 ;
-    %delay 10, 0;
-    %load/vec4 v0x7fa2f942c150_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c150_0, 0, 1;
-    %jmp T_1.2;
-    %end;
-    .thread T_1;
-    .scope S_0x7fa2f94081a0;
-T_2 ;
-    %pushi/vec4 0, 0, 16;
-    %store/vec4 v0x7fa2f942c210_0, 0, 16;
-    %wait E_0x7fa2f9415e20;
-    %pushi/vec4 65535, 0, 16;
-    %store/vec4 v0x7fa2f942c210_0, 0, 16;
-    %pushi/vec4 8, 0, 32;
-T_2.0 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_2.1, 5;
-    %jmp/1 T_2.1, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %wait E_0x7fa2f9416e90;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v0x7fa2f942c4d0_0, 0, 1;
-    %wait E_0x7fa2f9415f70;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c4d0_0, 0, 1;
-    %load/vec4 v0x7fa2f942c210_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c210_0, 0, 16;
-    %jmp T_2.0;
-T_2.1 ;
-    %pop/vec4 1;
-    %load/vec4 v0x7fa2f942c560_0;
-    %pad/u 32;
-    %pushi/vec4 1, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %load/vec4 v0x7fa2f942c350_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.2, 8;
-    %vpi_call 2 43 "$display", "Test failed!" {0 0 0};
-T_2.2 ;
-    %pushi/vec4 65535, 0, 16;
-    %store/vec4 v0x7fa2f942c6c0_0, 0, 16;
-    %pushi/vec4 8, 0, 32;
-T_2.4 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_2.5, 5;
-    %jmp/1 T_2.5, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %wait E_0x7fa2f9416e90;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v0x7fa2f942c400_0, 0, 1;
-    %wait E_0x7fa2f9415f70;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c400_0, 0, 1;
-    %load/vec4 v0x7fa2f942c2a0_0;
-    %load/vec4 v0x7fa2f942c6c0_0;
-    %cmp/ne;
-    %jmp/0xz  T_2.6, 6;
-    %vpi_call 2 52 "$display", "Test failed!" {0 0 0};
-T_2.6 ;
-    %load/vec4 v0x7fa2f942c6c0_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c6c0_0, 0, 16;
-    %jmp T_2.4;
-T_2.5 ;
-    %pop/vec4 1;
-    %load/vec4 v0x7fa2f942c560_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %load/vec4 v0x7fa2f942c350_0;
-    %pad/u 32;
-    %pushi/vec4 1, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.8, 8;
-    %vpi_call 2 57 "$display", "Test failed!" {0 0 0};
-T_2.8 ;
-    %pushi/vec4 5, 0, 32;
-T_2.10 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_2.11, 5;
-    %jmp/1 T_2.11, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %wait E_0x7fa2f9416e90;
-    %jmp T_2.10;
-T_2.11 ;
-    %pop/vec4 1;
-    %pushi/vec4 4660, 0, 16;
-    %store/vec4 v0x7fa2f942c210_0, 0, 16;
-    %pushi/vec4 8, 0, 32;
-T_2.12 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_2.13, 5;
-    %jmp/1 T_2.13, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %wait E_0x7fa2f9416e90;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v0x7fa2f942c4d0_0, 0, 1;
-    %wait E_0x7fa2f9415f70;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c4d0_0, 0, 1;
-    %load/vec4 v0x7fa2f942c210_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c210_0, 0, 16;
-    %jmp T_2.12;
-T_2.13 ;
-    %pop/vec4 1;
-    %load/vec4 v0x7fa2f942c560_0;
-    %pad/u 32;
-    %pushi/vec4 1, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %load/vec4 v0x7fa2f942c350_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.14, 8;
-    %vpi_call 2 69 "$display", "Test failed!" {0 0 0};
-T_2.14 ;
-    %pushi/vec4 4660, 0, 16;
-    %store/vec4 v0x7fa2f942c6c0_0, 0, 16;
-    %pushi/vec4 8, 0, 32;
-T_2.16 %dup/vec4;
-    %pushi/vec4 0, 0, 32;
-    %cmp/s;
-    %jmp/1xz T_2.17, 5;
-    %jmp/1 T_2.17, 4;
-    %pushi/vec4 1, 0, 32;
-    %sub;
-    %wait E_0x7fa2f9416e90;
-    %pushi/vec4 1, 0, 1;
-    %store/vec4 v0x7fa2f942c400_0, 0, 1;
-    %wait E_0x7fa2f9415f70;
-    %pushi/vec4 0, 0, 1;
-    %store/vec4 v0x7fa2f942c400_0, 0, 1;
-    %load/vec4 v0x7fa2f942c2a0_0;
-    %load/vec4 v0x7fa2f942c6c0_0;
-    %cmp/ne;
-    %jmp/0xz  T_2.18, 6;
-    %vpi_call 2 78 "$display", "Test failed!" {0 0 0};
-T_2.18 ;
-    %load/vec4 v0x7fa2f942c6c0_0;
-    %inv;
-    %store/vec4 v0x7fa2f942c6c0_0, 0, 16;
-    %jmp T_2.16;
-T_2.17 ;
-    %pop/vec4 1;
-    %load/vec4 v0x7fa2f942c560_0;
-    %pad/u 32;
-    %pushi/vec4 0, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %load/vec4 v0x7fa2f942c350_0;
-    %pad/u 32;
-    %pushi/vec4 1, 0, 32;
-    %cmp/e;
-    %flag_get/vec4 4;
-    %inv;
-    %and;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_2.20, 8;
-    %vpi_call 2 83 "$display", "Test failed!" {0 0 0};
-T_2.20 ;
-    %vpi_call 2 85 "$finish" {0 0 0};
-    %end;
-    .thread T_2;
-    .scope S_0x7fa2f94081a0;
-T_3 ;
-    %vpi_func 2 89 "$test$plusargs" 32, "waves=1" {0 0 0};
-    %cmpi/ne 0, 0, 32;
-    %jmp/0xz  T_3.0, 4;
-    %vpi_call 2 90 "$dumpfile", "out/waves.vcd" {0 0 0};
-    %vpi_call 2 91 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x7fa2f94081a0 {0 0 0};
-    %vpi_func 2 92 "$test$plusargs" 32, "dump_fifo=1" {0 0 0};
-    %cmpi/ne 0, 0, 32;
-    %jmp/0xz  T_3.2, 4;
-    %vpi_call 2 93 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 0> {0 0 0};
-    %vpi_call 2 94 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 1> {0 0 0};
-    %vpi_call 2 95 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 2> {0 0 0};
-    %vpi_call 2 96 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 3> {0 0 0};
-    %vpi_call 2 97 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 4> {0 0 0};
-    %vpi_call 2 98 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 5> {0 0 0};
-    %vpi_call 2 99 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 6> {0 0 0};
-    %vpi_call 2 100 "$dumpvars", 32'sb00000000000000000000000000000000, &A<v0x7fa2f942ba20, 7> {0 0 0};
-T_3.2 ;
-T_3.0 ;
-    %end;
-    .thread T_3;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "fifo_tb.v";
-    "simple_fifo.v";

out/waves.vcd

@@ -1,457 +0,0 @@
-$date
-	Mon May 22 18:16:34 2017
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1s
-$end
-$scope module fifo_tb $end
-$var wire 1 ! full $end
-$var wire 1 " empty $end
-$var wire 16 # data_out [15:0] $end
-$var reg 1 $ clk $end
-$var reg 16 % data_in [15:0] $end
-$var reg 1 & fifo_pop $end
-$var reg 1 ' fifo_push $end
-$var reg 1 ( reset_n $end
-$var reg 16 ) tmp [15:0] $end
-$scope module dut $end
-$var wire 1 $ clk $end
-$var wire 16 * data_in [15:0] $end
-$var wire 1 & pop $end
-$var wire 1 ' push $end
-$var wire 1 ( reset_n $end
-$var reg 16 + data_out [15:0] $end
-$var reg 1 " empty $end
-$var reg 1 ! full $end
-$var reg 3 , rd_ptr [2:0] $end
-$var reg 3 - wr_ptr [2:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 . \data[0] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 / \data[1] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 0 \data[2] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 1 \data[3] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 2 \data[4] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 3 \data[5] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 4 \data[6] [15:0] $end
-$upscope $end
-$upscope $end
-$scope module fifo_tb $end
-$scope module dut $end
-$var reg 16 5 \data[7] [15:0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-bx 5
-bx 4
-bx 3
-bx 2
-bx 1
-bx 0
-bx /
-bx .
-bx -
-bx ,
-bx +
-b0 *
-bx )
-1(
-x'
-x&
-b0 %
-0$
-bx #
-x"
-x!
-$end
-#10
-1"
-0!
-b0 -
-b0 ,
-1$
-#20
-0$
-#30
-1$
-#40
-b1111111111111111 %
-b1111111111111111 *
-0(
-0$
-#50
-0"
-b1111111111111111 .
-b1 -
-1'
-1$
-#60
-b0 %
-b0 *
-0'
-0$
-#70
-b0 /
-b10 -
-1'
-1$
-#80
-b1111111111111111 %
-b1111111111111111 *
-0'
-0$
-#90
-b1111111111111111 0
-b11 -
-1'
-1$
-#100
-b0 %
-b0 *
-0'
-0$
-#110
-b0 1
-b100 -
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simple_fifo.v

@@ -1,3 +1,4 @@
+`timescale 100ps/1ps
 /*
 * DEPTH must be a power of 2
 */
@@ -22,7 +23,7 @@ reg [$clog2(DEPTH)-1:0] wr_ptr;
 reg [WIDTH-1:0] data [DEPTH-1:0];
 
 always @(posedge clk) begin
-  if (reset_n) begin
+  if (~reset_n) begin
     rd_ptr <= 0;
     wr_ptr <= 0;
     full <= 0;
@@ -34,10 +35,8 @@ always @(posedge clk) begin
       wr_ptr = wr_ptr + 1;
       if (wr_ptr == rd_ptr) begin
         full <= 1'b1;
-        empty <= 1'b0;
       end
       else begin
-        full <= 1'b0;
         empty <= 1'b0;
       end
     end
@@ -45,12 +44,10 @@ always @(posedge clk) begin
       data_out <= data[rd_ptr];
       rd_ptr = rd_ptr + 1;
       if (wr_ptr == rd_ptr) begin
-        full <= 1'b0;
         empty <= 1'b1;
       end
       else begin
         full <= 1'b0;
-        empty <= 1'b0;
       end
     end
   end

test

@@ -1 +0,0 @@
-./out/sim +waves=1 +dump_fifo=1