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@@ -33,22 +33,14 @@ always @(posedge clk) begin
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33
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33
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if (push & ~full) begin
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34
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34
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data[wr_ptr] <= data_in;
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35
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35
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wr_ptr = wr_ptr + 1;
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36
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- if (wr_ptr == rd_ptr) begin
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37
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- full <= 1'b1;
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38
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- end
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39
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- else begin
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40
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- empty <= 1'b0;
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41
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- end
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36
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+ if (wr_ptr == rd_ptr) full <= 1'b1;
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37
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+ else empty <= 1'b0;
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42
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38
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end
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43
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39
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if (pop & ~empty) begin
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44
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40
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data_out <= data[rd_ptr];
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45
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41
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rd_ptr = rd_ptr + 1;
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46
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- if (wr_ptr == rd_ptr) begin
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47
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- empty <= 1'b1;
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48
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- end
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49
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- else begin
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50
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- full <= 1'b0;
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51
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- end
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42
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+ if (wr_ptr == rd_ptr) empty <= 1'b1;
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43
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+ else full <= 1'b0;
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52
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44
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end
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53
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45
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end
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54
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46
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end
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